Nice data, thanks for doing that and posting the results in an informative way.
It depends on the crystal circuit.
The way the trim works is selecting additional capacitance on the XTAL pins. The added capacitance is a fixed value based on the manufacture of the DW1000 chip, described as being 7.75 pF maximum value in the datasheet, which is 0.25 pF per step over 31 steps. The selectable capacitors are thus 4 pF, 2 pF, 1 pF, 0.5 pF, and 0.25 pF, each enabled by one of the bits in XTALT.
38.4 MHz crystals can be had with loading capacitance parameters from 4 pF to 22 pF. If your crystal has a 4 pF loading value, then a 7.75 pF adjustment is much larger shift in the crystal’s frequency than if the crystal has a 22 pF loading value.
The adjustment step depends on the crystal chosen, which affects the loading caps put on the PCB, and thus affects the adjustment range of XTALT.
Section 5.14 of the DW1000 datasheet covers this topic and says:
“The type of crystal used and the value of the loading capacitors will affect the crystal trim step size and the total trimming range.”
They give formulas to compute what range and step you will get for a particular setup.
For those designing their own boards, what value is ideal for the crystal load capacitance?
If you want fine adjustment with XTALT, then selecting a crystal with high loading, say 20 pF, results in the finest adjustment, but more limited range. You will want to get a 10 ppm crystal to be sure you are “in range”. A downside to the high loading is increased energy usage since the signal is being loaded by 40 pF capacitors on each crystal pin. This is likely around 5 mW power usage for that loading.
If you want lowest power and don’t care about fine adjustment via XTALT, then select a crystal with low loading. Now it can also be lower tolerance since you have a bigger adjustment range, so perhaps 30 ppm works. The power savings are something as an 8 pF load crystal uses about 2 mW of power.
You may think the 3 mW of power savings isn’t much given the DW1000 power usage during receive and transmit is 100s of mW. But, if you duty cycle the DW1000 between SLEEP or DEEPSLEEP and TX/RX modes (as any good tag design will do to save battery), there’s a 2-4 ms period before the DW1000 can operate where it is starting the crystal oscillator (INIT phase). Those extra 3 mW of power exists during that time. So you have, say, 3 ms of an extra 3 mW, 9 uJ extra due to high crystal load. The energy you spend sending a blink, say 100 us long and 200 mW, is 20 uJ. Now it doesn’t seem so small in comparison, about half the transmit energy was lost in crystal loading in a tag that sleeps between blinks.
The higher load capacitors also improve the crystal robustness against noise injection and are somewhat more stable. It is harder to push the signal around if it operates under more load, and small changes in capacitance (which can occur with temperature changes) don’t upset the frequency as much.
Mike Ciholas, President, Ciholas, Inc
3700 Bell Road, Newburgh, IN 47630 USA
mikec@ciholas.com
+1 812 962 9408