We’re running a PDoA setup for localization as follows:
1 EVB1000 running the two-way ranging firmware, as an anchor
A custom PCB with 5 DWM1000 modules, all running under the same 38.4MHz clock from an oscillator and a clock buffer tree. One module is running the two-way ranging firmware as tag, and other 4 DWM1000 modules configured after the tag module send out the poll, to listen to the response from EVB1000 anchor. The modules are separated by wavelength/2.
Our goal is to obtain the AOA(angle of arrival) of the anchor to the PCB (tag and array of DWM1000s). So we extract out the CIR from accumulators in the array of 5 DWM1000 modules, find the FP(first peak) index and find the phase from the accumulator sample at that FP index. Then we calculate AOA from the phase difference across DWM1000 modules.
The idea of this setup is pretty similar to the PDoA kit. However one issue we have in our setup is that we observe a nonzero phase difference across adjacent chips when the anchor and our board are facing directly to each other (0 degree AOA). And we found out In order to calculate a reasonable AOA, this offset at 0 degree has to be subtracted out from all phase differences for all angles.
As we did more testing, we find out this offset is relatively consistent after the PCB is powered and stay powered. (Small drifts still exist). And once we power off the PCB and power on again, this offset changes to a random value.
Any ideas on where this offset come from? We thought it might be the PLL in DW1000 that’s causing this offset? However for the PDoA kit we didn’t see it need to be calibrated at 0 degree. How does the PDoA kit solve this offset problem?
And is the SYNC input on DW1000 related to / could help on this offset?
IN PDoA the offset to 0 degree is also exist. How did you not noticed a big button in the gui called “Calibration”?
2.sync pin of dw1000 is used to make offset predictable. It should be obvious from schematics and the code.
So you can calibrate once and all the rest start-ups the diff would be the same.
Thanks for your reply! I did notice the calibration button and the kit subtract this offset during calculation in the source code, but our PDoA kit works reasonably well out of the box so we never used it… I guess the kit might be precalibrated in the factory?
But this also means this 0 degree offset is stable after module power off. But on our board it is not. It actually varies a lot after module power off then power on (we observe it being almost random). I wonder if there is some other trick in the hardware / software that we didn’t consider. (Maybe the SYNC)?
Could you elaborate on the functionality of SYNC? The user manual of DW1000 did not really explain what’s going on when SYNC pulse is received by DW1000. Does it sync the sampling clock (so will have a direct effect to the phase offset), or the system time in DW1000? If you could point us where we can read more on how the PLL / SYNC works in DW1000 that would be really great!
Hi Scott’s,
Yes, the sync pin is what you have missed… Please search its description in the DW1000 User Manual. IN PDoA kit the sync of two chips executes only once on the start-up of the Node application.
When you are syncing two chips, you are resetting both counters and chips starts clocking synchronously. In the hw design it is recommended having tcxo on the Node side and crystal on the tag, such tags can auto trim Xtal for correct operation with PDoA node.
Advices:
Try having lengths of signals from clock buffer to both chips as similar in length as you can.
Copy the 2eyes antenna design as good as you can, including the stack. Consult with Decawave.
Answering your question wrt Calibration button: variations during process in DW1000 chip, (i think it is a finest part of the antenna delay), would always introduce the offset in between two chip toa differences. You lucky having the PDoA kit with small offset. But that is not always true. I have a kit with 87 deg offset for example. It works perfectly, but it had require calibration on the beginning.