DWM3000 Status register values / error codes

Wireless Connectivity Ultra-Wideband
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1

Hi,

I recently received a set of DWS3000 Arduino shields. I am using them together with the STM Nucleo F429ZI. The normal setup and the examples do work fine, but I managed to change some TX settings that started some RX errors on the other side.
I wanted to further understand how those errors might occur, but I could not find any explanations for the different error codes in the status register. I checked with the SYS_STATUS_ALL_RX_ERR and realized that the Bit mask SYS_STATUS_RXSTO_BIT_MASK matches my error.

Is there any documentation available what those errors actually mean? I could not find them in the documentation pdfs or the source code. Any help is appreciated. Thank you.

Kind regards
Alexander

2

Going by this post from last week the user manual for the DW3000 should be out very soon. That should give definitions for all of the status register bits.

3

That would be great.

4

I have not seen any updates on this.
One thing that I managed to understand is that most system status codes are copied from the DW1000 codes and there they have been documented. So here’s a list of RX related status codes that where I copied the meaning from the DW1000:

#define SYS_STATUS_ID                        0x44                 
#define SYS_STATUS_LEN                       (4U)                
#define SYS_STATUS_MASK                      0xFFFFFFFFUL        
#define SYS_STATUS_ARFE_BIT_OFFSET           (29U)               
#define SYS_STATUS_ARFE_BIT_LEN              (1U)                
#define SYS_STATUS_ARFE_BIT_MASK             0x20000000UL   /* Automatic Frame Filtering rejection */
#define SYS_STATUS_CPERR_BIT_OFFSET          (28U)               
#define SYS_STATUS_CPERR_BIT_LEN             (1U)                
#define SYS_STATUS_CPERR_BIT_MASK            0x10000000UL   /* COULD BE:  Mask Transmit Buffer Error event */
#define SYS_STATUS_HPDWARN_BIT_OFFSET        (27U)               
#define SYS_STATUS_HPDWARN_BIT_LEN           (1U)                
#define SYS_STATUS_HPDWARN_BIT_MASK          0x8000000UL    /* Mask Half Period Delay Warning event */
#define SYS_STATUS_RXSTO_BIT_OFFSET          (26U)               
#define SYS_STATUS_RXSTO_BIT_LEN             (1U)                
#define SYS_STATUS_RXSTO_BIT_MASK            0x4000000UL    /* Mask Receive SFD timeout event   */
#define SYS_STATUS_PLL_HILO_BIT_OFFSET       (25U)               
#define SYS_STATUS_PLL_HILO_BIT_LEN          (1U)                
#define SYS_STATUS_PLL_HILO_BIT_MASK         0x2000000UL     /* Mask Clock PLL Loosing Lock warning event    */
#define SYS_STATUS_RCINIT_BIT_OFFSET         (24U)               
#define SYS_STATUS_RCINIT_BIT_LEN            (1U)                
#define SYS_STATUS_RCINIT_BIT_MASK           0x1000000UL    /*COULD BE: RF PLL Losing Lock */
#define SYS_STATUS_SPIRDY_BIT_OFFSET         (23U)               
#define SYS_STATUS_SPIRDY_BIT_LEN            (1U)                
#define SYS_STATUS_SPIRDY_BIT_MASK           0x800000UL      /*COULD BE:  SLEEP to INIT */
#define SYS_STATUS_RXPTO_BIT_OFFSET          (21U)               
#define SYS_STATUS_RXPTO_BIT_LEN             (1U)                
#define SYS_STATUS_RXPTO_BIT_MASK            0x200000UL    /* Preamble detection timeout */
#define SYS_STATUS_RXOVRR_BIT_OFFSET         (20U)               
#define SYS_STATUS_RXOVRR_BIT_LEN            (1U)                
#define SYS_STATUS_RXOVRR_BIT_MASK           0x100000UL   /* Receiver Overrun */
#define SYS_STATUS_VWARN_BIT_OFFSET          (19U)               
#define SYS_STATUS_VWARN_BIT_LEN             (1U)                
#define SYS_STATUS_VWARN_BIT_MASK            0x80000UL    /* ??? */
#define SYS_STATUS_CIAERR_BIT_OFFSET         (18U)               
#define SYS_STATUS_CIAERR_BIT_LEN            (1U)                
#define SYS_STATUS_CIAERR_BIT_MASK           0x40000UL   /* COULD BE:  Mask leading edge detection processing error event   */
#define SYS_STATUS_RXFTO_BIT_OFFSET          (17U)               
#define SYS_STATUS_RXFTO_BIT_LEN             (1U)                
#define SYS_STATUS_RXFTO_BIT_MASK            0x20000UL   /* Mask Receive Frame Wait Timeout event    */
#define SYS_STATUS_RXFSL_BIT_OFFSET          (16U)               
#define SYS_STATUS_RXFSL_BIT_LEN             (1U)                
#define SYS_STATUS_RXFSL_BIT_MASK            0x10000UL   /* Mask receiver Reed Solomon Frame Sync Loss event */
#define SYS_STATUS_RXFCE_BIT_OFFSET          (15U)               
#define SYS_STATUS_RXFCE_BIT_LEN             (1U)                
#define SYS_STATUS_RXFCE_BIT_MASK            0x8000U  /* Receiver FCS (Frame Check Sequence) Error */
#define SYS_STATUS_RXFCG_BIT_OFFSET          (14U)               
#define SYS_STATUS_RXFCG_BIT_LEN             (1U)                
#define SYS_STATUS_RXFCG_BIT_MASK            0x4000U /* Receiver FCS (Frame Check Sequence) Good */
#define SYS_STATUS_RXFR_BIT_OFFSET           (13U)               
#define SYS_STATUS_RXFR_BIT_LEN              (1U)                
#define SYS_STATUS_RXFR_BIT_MASK             0x2000U   /* Mask receiver data frame ready event */
#define SYS_STATUS_RXPHE_BIT_OFFSET          (12U)               
#define SYS_STATUS_RXPHE_BIT_LEN             (1U)                
#define SYS_STATUS_RXPHE_BIT_MASK            0x1000U   /* Mask receiver PHY header error event */
#define SYS_STATUS_RXPHD_BIT_OFFSET          (11U)               
#define SYS_STATUS_RXPHD_BIT_LEN             (1U)                
#define SYS_STATUS_RXPHD_BIT_MASK            0x800U    /* Mask receiver PHY header detect event    */
#define SYS_STATUS_CIADONE_BIT_OFFSET       (10U)               
#define SYS_STATUS_CIADONE_BIT_LEN          (1U)                
#define SYS_STATUS_CIADONE_BIT_MASK         0x400U   /*Could be:  Mask LDE (leading edge detection) processing done event   */
#define SYS_STATUS_RXSFDD_BIT_OFFSET         (9U)                
#define SYS_STATUS_RXSFDD_BIT_LEN            (1U)                
#define SYS_STATUS_RXSFDD_BIT_MASK           0x200U   /* Mask receiver SFD detected event */
#define SYS_STATUS_RXPRD_BIT_OFFSET          (8U)                
#define SYS_STATUS_RXPRD_BIT_LEN             (1U)                
#define SYS_STATUS_RXPRD_BIT_MASK            0x100U  /* Mask receiver preamble detected event    */
5

The DW3000 user manual came out over two weeks ago. It’s available from https://www.decawave.com/wp-content/uploads/2021/05/DW3000-User-Manual-1.pdf

Section 8.2.2.14, page 90 onwards, gives details of the status register.

6

Ah that’s great. Where did you find it? It was not listed at the product pages DWM3000 Module - Decawave
nor on Qorvo site for the DW3000 products

7

It’s listed at Design Center → DW3000IC (but only there)