I want to interface the device to a 2.1V CPU. Now I can do this if I use the 2.8V option, but which supply ids this IO based on VDDAON or VDD3V3. I assume it would be better to leave main supply at 3V3 to get make power delivery on RF
Only practical way is to use a voltage translator for the logic signals so that the processor operates on 2.1 volts and the DW1000 operates at 3.3 volts.
One such option are 74AUP1T parts which, despite operating from 3.3 volts, will handle input logic operating from 2.1 volts. So a few AUP1T gates can manage to translate SCLK, CS, MOSI, WAKE, etc. There are other translators you can use as well, the AUP1T are just low power in high speed circuits.
If the processor is an ST type (STM32…), most of their inputs are tolerant to voltages over VDD, so they don’t need a translator on the input. The 3.3 volt logic of the DW1000 will go right in and becomes 0 or 1 with a 2.1 volt VDD rail on the processor. This would work for MISO, IRQ, EXTON, etc.
For processors not tolerant to voltages over VDD, you will need a translator going the other way as well.
An 8 bit auto bidirectional translator is the ON Semi FXLA108.
It isn’t good with pullups, but with full drive (as SPI signals are), it works just fine and is relatively inexpensive. This one part can handle 8 signals, which is likely enough for a DW1000 system. You do need to analyze the delays introduced by the translator. There’s usually no problem for outbound signals like MOSI since both the SCLK and MOSI suffer roughly the same outbound delay. The real issue is MISO which is two translator delays slowed down relative to SCLK at the processor.
Mike Ciholas, President, Ciholas, Inc
3700 Bell Road, Newburgh, IN 47630 USA
mikec@ciholas.com
+1 812 962 9408
Thanks for reply. But datasheet specifies 0.75 *VDD, which for 3.3V is 2.475V for min input high level
That’s why you use a voltage translator chip, so it produces the full voltage swing. A processor with a 2.1 volt drive (as you have) is thus converted to a 3.3 volt swing (which the DW1000 can use).
Mike Ciholas, President, Ciholas, Inc
3700 Bell Road, Newburgh, IN 47630 USA
mikec@ciholas.com
+1 812 962 9408
Ah thanks, my mistake, misunderstood your previous reply. You meant the outputs to the CPU would be ok, but not from the CPU to the chip.
We are now looking at designing in the chip instead of the module. I noticed that VDDIO, is derived from VDDIOA. The datasheet specs that that can run at 2.8V. Is it acceptabel to power this pin at 2.8V to get lower voltage IO logic interface on SPI without affecting the RX LNA and TX PA. The reason is at 2.8V, if the 0.7 VDD transition level applies to the SPI interval, then we can operate the CPU at 2V, without the need for addition buffers.
There are many pros and cons to that change. The biggest challenge is that you need to have a much higher skill set to design at the chip level. Another one is regulatory approvals.
At Ciholas, we design almost everything at the chip level for the benefits that provides. Namely, exact setup we want, better antennas, change in physical form, etc. But this takes a skilled design team to accomplish.
I would not ditch the module solely for an IO voltage incompatibility. That’s creating a whole new set of complexities. And, ultimately, you still have the same IO voltage issue to deal with since that comes from the DW1000 chip itself.
Now if you want a custom design at the chip level and are willing to hire an expert to do it, then you can get what you want, but it does cost money to do that. The final result will out perform the module significantly, if your chosen expert knows what they are doing.
You are playing a dangerous game with logic voltage levels. I predict severe frustration in your future with this tactic.
Logic signals work because there is margin between the minimum output high and the maximum input high that is accepted. If the DW1000 is operated at 2.8 VDD, then 0.7 * VDD is 1.96 volts. If your processor is at 2.1 V VDD, then it might just barely reach that voltage. But if you consider static and dynamic loads, it won’t. You need typically at least 0.4 volt margin from VDD to output high to account for that. So a 2.1 V VDD processor is going to output 1.7 volts or so under actual dynamic use. That doesn’t meet the input high requirements of the DW1000.
One thing to realize is that the SPI bus is really an analog signal comprised of RC networks. R from the driver resistance, C from the trace an pin capacitance. If you want the SPI bus to go fast, then you have to constantly charge and discharge those RC networks, which mean they don’t actually get all the way to the power rails during a transfer. If the traces are long, then you start to get transmission line effects as well.
Put down a voltage translator chip. Or run your processor at a higher voltage. Now everything works as it should.
Mike Ciholas, President, Ciholas, Inc
3700 Bell Road, Newburgh, IN 47630 USA
mikec@ciholas.com
+1 812 962 9408
Thankyou for your reply.
I have no issues with designing at chip level, I have been designing in wireless chips for over 10 years, but thanks for your concern.
I have found a neat solution to overcome the level translation (you have to understand space and power is a premium - we design the smallest GSM trackers in the world with built in wifi, bluetooth, Lora and now UWB thanks to your chip. I design everything myself including schematics through to layout and coordinate assembly either in China or UK - So I am okay with your chip - intrigued by some of your design decisions - but data package is complete and I like that.
We only started prototyping last week with a module and its all up and running on one of our pcbs. So I am now going to chip level - costs is also a large key factor as well and at $5 for your chip it provides a neat solution as we can now provide indoor location and positioning with our units.